As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between elements (i.e., the pitch) of a device is less than the pitch that can be manufactured using traditional optical masks and photolithography equipment. One approach used to achieve higher resolution in smaller nodes, e.g., 20 nm or smaller devices, is to use multiple pattern lithography. For example, sidewall imaging techniques have been used to scale the spaces and features of a device. For example, in sidewall imaging techniques, dummy lines (e.g., at a minimum available pitch) are first formed, followed by formation of sidewall aligned spacers on the dummy lines. The dummy lines are removed while leaving the spacers, and then the spacers are used as patterning masks to transfer the desired pattern to underlying layers. In this way, line spacing at approximately half the minimum pitch can be achieved.
The use of additional materials (e.g., reverse material layers) for additional lithography patterning and cutting may be performed on the spacers prior to the removal of the dummy lines. This additional patterning/cutting allows for greater variation and/or more complex patterns to be formed in semiconductors for back end of line (BEOL) processes with small pitches. However, traditional techniques for additional patterning/cutting rely on multiple steps, which increases manufacturing cost. Also, many of these techniques can increase the parasitic performance of the device.